Most sample-data analog circuits such as switched-capacitor filters, analog-to-digital converters, and delta-sigma modulators require operational amplifiers to process the signal. Consider a switched-capacitor integrator example shown in FIG. 2. First, the switches S11 and S13 are closed so that the input voltage vin is sampled on the sampling capacitor CS1. Next, the switches S11 and S13 are opened and S12 and S14 are closed. This operation transfers the charge in the sampling capacitor CS1 to the integrating capacitor CI1. The output voltage, vout, of a first integrator 1100 is typically sampled by another sample-data circuit, for example, another switched-capacitor integrator.
In the circuit shown in FIG. 2, the circuit consisting of switches S21, S22, S23, S24, and a second sampling capacitor CS2 comprise a part of the second switched-capacitor integrator. The output voltage, vout, of the first integrator 10 is sampled on the second sampling capacitor CS2 by closing switches S21 and S23.
An example of a timing diagram is shown in FIG. 3. The clock signal has two non-overlapping phases φ1 and φ2. The phase φ1 is applied to switches S11, S13, S21, and S23, and phase φ2 is applied to switches S12, S14, S22, and S24. With this timing, the circuit performs non-inverting discrete integration with full clock delay. The waveforms at the output of the integrator, vout, and at the virtual ground node 100, v1, are also shown in FIG. 3. Different clock phasing arrangements yield different responses from the integrator. For example, if φ1 is applied to switches S11, S13, S22, and S24, and phase φ1 is applied to switches S12, S14, S21, and S23, the circuit performs non-inverting integration with half-clock delay.
For an accurate integration of the input signal, v1 must be driven as close to ground as possible. In order to accomplish this, the operational amplifier must provide sufficient open-loop gain and low noise. In addition, for fast operation, the operational amplifier 10 of FIG. 2 must settle fast.
In FIG. 3, the voltage v1 is shown to settle back to ground after a disturbance when the sampling capacitor CS1 is switched to Node 100 by closing S12 and S14. In addition to high open-loop gain and fast settling time, operational amplifiers must provide large output swing for high dynamic range. As the technology scales, it becomes increasingly difficult to achieve these characteristics from operational amplifiers. The primary factors that make the operational amplifier design difficult are low power supply voltages and low device gain.
As noted above, accurate output voltage can be obtained if Node 100 in FIG. 2 is maintained precisely at ground. However, in sample-data circuits, the only point of time accurate output voltage is required is at the instant the output voltage is sampled by another sampling circuit. Thus, it is not necessary to maintain the voltage at Node 100 at ground all the time.
It is further noted that delays in the detectors of sample-data circuits may cause errors in the operation thereof. Moreover, it is noted that performance parameters such as speed, accuracy, and power consumption of sample-data circuits depend upon the design of zero crossing detectors.
Therefore, it is desirable to provide a sample-data circuit that maintains the proper level at the virtual ground node at the instant the output voltage is sampled by another sampling circuit, substantially eliminates the errors caused by delays, and optimizes the performance parameters such as speed, accuracy, and power consumption of the sample-data circuit.
Moreover, it is desirable to provide a sample-data circuit that maintains the proper level at the virtual ground node at the instant the output voltage is sampled by another sampling circuit and provides differential signal paths for sample-data circuits, substantially eliminates the errors caused by delays, and optimizes the performance parameters such as speed, accuracy, and power consumption of the sample-data circuit.
Furthermore, it is desirable to provide a sample-data circuit that reduces the effect of power supply, substrate, and common-mode noise by symmetric differential signal processing, substantially eliminates the errors caused by delays, and optimizes the performance parameters such as speed, accuracy, and power consumption of the sample-data circuit.
Also, it is desirable to provide a sample-data circuit that increases the signal range by incorporating differential signal paths, substantially eliminates the errors caused by delays, and optimizes the performance parameters such as speed, accuracy, and power consumption of the sample-data circuit.